System for automatic correction of burst-errors



Nov. l1, 1969 SYSTEM FOR AUTOMATIC CORRECTION OF BURST-ERRORS C. V. SRINIVASAN Filed Jan. 20, 1966 8 Shee 'cs-Sheet 1 THE lfcdllk 577 d 677:5 w ma 1F l mummia/w :facu/r w22 moese a www INVENTOR. I4/ro e 1./ .5km/l 4x4/v Hierna/ Nov. l1, 1969 c. v. sRlNlvAsAN SYSTEM FOR AUTOMATIC CORRECTION 0F BURST-ERRORS 8 Sheets-Sheet 2 Filed Jan. 20, 1966 w w W |l Il I ,540 may Min/MY @we wam 4 /A/ fas/ww ffm/awa ra 1 u wwe/f ,415

Appxfs: 056095K I/r' INE/7170K.

F l 4l SYSTEM FOR AUTOMATIC CORRECTION OF BURST-ERRORS Filed Jan. 20, 1966 Nov. l1, 1969 c. v. sRlNlvAsAN 8 Sheets-Sheet 5 KED ONLYWEMiY 30 ma M H c f w. i Se x 11.! :@IINVENTOR. 'l//r Ek/Mau Nov. 11, 1969 c. v. sRlNlvAsAN 3,478,313

SYSTEM Foa AUTOMATIC CORRECTION oF BURST-ERRORS Filed Jan. 20, 1966 8 Sheets-Sheet 4 l l I Aaxiss i 04721 ,'r-ca/m'A/umffssfa g :far/0M I :fana/v g 'Vf/"MWF" l l l 1 W F 6B ,4pm-,e /22 ea wie //rs me? ni-lame# e sheets-sheet s Nov. 1l, 1969 c. v. sRxNlvAsAN I SYSTEM FOR AUTOMATIC CORRECTION OF' BURST-ERRORS Filed Jan. 20, 1966 ms; m Nw.. v+m-Hw Nov. 11, 1969 c. v. sRlNlvAsAN 3,473,313

SYSTEM FOR AUTOMATICl CORRECTION OF BURST-ERRORS Filed Jan. 20, 1966 8 Sheets-Sheet 6 Ff9.l0a. l@ .10b

INVENTOR. C'f//r ,e [LWN/V54 Nov. l1, 1969 c.v.sR1N-|vAsAN SYSTEM FOR AUTOMATIC CORRECTION OF BURST-ERRORS v INVENTOR ffl/raak l/Je/N/wsm/ 8 Sheets-Sheet 'I Afin/'nell Nov. 11, 1969 c. v. sRlNlvAsAN 3,478,313

SYSTEM FOR AUTOMATIC CORRECTION 0F BURST-ERRORS Filed Jan. 20, 1966 8 Sheets-Sheet 8 .y w .,Svu wnlHHTl Rw, a w. kvk mnu mM M E .SQK mm y A Z .QNN M r W f. w

b. SQN QN @.N Q @bx CS kuw #GQ wbmw bs C bwv.. WMNIQ 1w. flaw. ICQ. IW 1w IW. Fm M MN .Q .mi vu &\\ BN United States Patent Oce Patented Nov. 11, 1969 3,478,313 SYSTEM FOR AUTOMATIC CORRECTION OF BURST-ERRORS Chitoor V. Srinivasan, Princeton, NJ., assignor to RCA Corporation, a corporation of Delaware Filed Jan. 20, 1966, Ser. No. 521,910 Int. Cl. G08b 29/00; G06f 11/00 U.S. Cl. S40-146.1 5 Claims ABSTRACT OF THE DISCLOSURE This invention relates to information handling and transmission and particularly to burst-error correction systems for binary data.

A general object of the invention is to provide a coding arrangement for transmitted data and a decoding arrangement for received data which together automatically correct bursts of errors in the data. v

Another object of the invention is to provide a new and improved error correcting code which is relatively economical in that a relatively small number of check digits is employed for a relatively large number of information digits and in that this relatively small number of check digits can correct error bursts of substantial length.

Another object of the invention is to provide bursterror correction systems which are suitable for use both in systems such as memory systems Where the bits may be transmitted in parallel and also in systems such as communications systems where the bits may be transmitted in serial fashion.

In the system of the invention, the information bits are arranged in sub-sets in accordance with some rules discussed in detail below and a check bit is generated for each such sub-set of information bits. The information and check bits are then transmitted in a certain order or grouping. At the receiving end of the system, the information and check bits are examined and a word known as a syndrome is generated. If there is anv error in the word, as received, the syndrome will contain one or more 1s in positions indicative of the information or check bit or bits which are in error. The system also includes means responsive to the syndrome for indicating whether an error has occurred during the transmission and, if so, the particular bit or bits which are in error. An error correcting circuit responsive to the last-named means automatically corrects for any such error or errors.

The invention is discussed in greater detail below and is shown in the following drawings of which:

FIGURE 1 is a block circuit diagram of a system according to the invention;

FIGURE 2 is a block circuit diagram of the check bit generating circuit of FIGURE 1;

FIGURE 3, is a block circuit diagram of the syndrome generating circuit of FIGURE 1;

FIGURE 4 is a block circuit diagram of one embodiment of an error indicating circuit according to the invention, this circuit also being a portion of the system of FIGURE 1;

7 FIGURE is a somewhat more detailed showing of lthe circuit of FIGURE 4;

FIGURE 6 is a block circuit diagram of another embodiment of an error indicating circuit according to the invention;

FIGURES 7, 8 and 9 are block circuit diagrams of the circuit within block 20 of FIGURE 1 for an embodiment of the invention in which decoder gates are employed for correcting errors;

FIGURES 10aa-10d show certain details of the circuit of FIGURE 7;

FIGURE 1l (on two sheets 11a and 11b) is a block circuit diagram of a system according to the invention in which the bits are transmitted and received in serial fashion; and

FIGURE 12 is a more detailed showing of the circuits within block 198 of FIGURE l1.

The circuits shown in the drawing include gates to which electrical signals indicative of binary digits (bits) are applied and which produce electrical signals indicative of bits. To simplify the discussion which follows, the bits themselves are sometimes referred to rather than the signals manifesting the bits.

In the discussion of the invention below, the term error applied to a bit of a binary word means that the bit does not have the same value at the input and output of a data transmission or storage channel. The term bursterror means that lthe errors in a binary word occur in a sub-string of adjacent bits. If the burst-error is of length a this implies that no sub-string of length a-l includes all the errors. Finally, when it is stated that a certain code can correct burst-errors of length a, this means that the system can correct for any one or more bits which are in error if these bits fall Within a group of a continuous bits.

The system of the present invention is illustrated in FIGURE l. To make the explanation somewhat easier to follow, a specic example, namely a system for transmitting n=36 information bits x1, x2 x36 is illustrated. However, this specific illustration is not to be taken as limiting the invention, as the concepts discussed herein are perfectly general. To show that this is so, a number of other examples are given later.

The system of FIGURE l includes a register 10 for storing the 36 information bits acl-x36. These bits are applied to a circuit 12 for generating check bits. As is discussed in more detail later, in the circuit 12 the information bits are subdivided into groups known as sub-sets S. In this particular case, there are k=9 sub-sets, and each sub-set has 8 bits. A check bit a is generated for each such sub-set. The rules defining how bits for each sub-set are chosen are discussed later.

The check bits from circuit 12 and the information bits from circuit 10 are applied to a circuit 14 which transmits these information and check bits. The transmitted word, in this particular example, consists of 9 segments E1 E9, where each segment contains 4 information bits and 1 check bit. The four information bits are adjacent bits taken from the group acl-x36 and the check bit is chosen from among the 9` check bits in a manner to be discussed later. The transmitted word is defined as W and consists of 45 bits w1, W2 w45. The letter w refers either to an information bit x or a check bit a. To give some examples, w1=x1, w5=a5,H

Wszxs, W45=a4- The word W is transmitted via a transmission channel 16. The word may be transmitted serially and this is usually the case in a communication system. Alternatively, the transmission channel may, in fact, be a memory or vthe like in which case the w bits may be transmitted o in parallel. As a third alternative, groups of the bits,

segment E. The present invention is applicable to all of these types of transmission.

The word W at the output end of the transmission channel may or may not be equal to the word W which is transmitted. If the two are equal, no errors have occurred during transmission. If the two are unequal, one or more errors has occurred during transmission.

The circuit 1S includes means for comparing the information and check bits in a certain way, as discussed in detail later, and for indicating, as a result of this comparison, whether or not there are any errors in W. As a result of this comparison, the means 18 generates a syndrome Z which is a 9 bit word. If there are no errors in W, the syndrome Z consists of all Os. If there is an error, then the syndrome contains one or more ones and, as will be shown in detail below, the position of the 1 or ls is indicative of the bit or bits which are in error. It should be mentioned here, as an aside, that there need not to be a one-tO-one correspondence between the number of ls in the syndrome and the number of bits in W which are in error.

The particular system illustrated in FIGURE l is capable of correcting for burst-errors of length g3. It will be shown later that there are 180 such single bursterrors which are possible and therefore 180 different syndromes are capable of identifying such errors.

The syndrome Z produced by the means 18 is applied to the means 20. The latter indicates whether or not there is an error and, if there is an error, the particular bit or bits in error. The output word F produced by circuit 20 is a 45 bit word and it contains Os in the bit positions having no errors and 1s in the bit positions having an error. For example, if the only error is in bit w1, F would be a 45 bit word starting with a 1 and following by 44 (ls.

The word F and the word W are applied to an error correcting circuit 22. This circuit may simply be a modulo 2 adder and it produces a corrected word at its output which is equal to W if the burst-error which has occurred is S3.

Check Bit Generation As mentioned above, the information bits are grouped in k sub-sets S1 Sk and a check bit is generated for each sub-set of information bits. The sub-sets S1 Sk are rows in a matrix [V] having k columns and k rows. The first column V1 of the matrix [V] consists of information bits having the subscripts l, 2 t, t 2, 1. Each succeeding ith column V1 Of the matrix consists of information bits having the subscripts [fu-DH1, f(i-1) (fi), t, (zi) .fo-1), [1( -1)-{1] cyclicly shifted down through rows, where i=1, 2 k; indicates an odd number of empty spaces; k is an odd integer; and t is less than k/Z. It should also be mentioned that, by defininition, when performing a cyclic downward shift through rows, the bits which are left over are placed at the top of the column. For example, if the last bit in a column is 9 and a column is shifted down through 1 row, the 9 will appear in the first row of the shifted column.

The table for 11:36 and k=9 appears below. As mentioned above, A in the table means that no bit is present and, in this particular case, represents only one space. (Table IX, at the end of the specification, gives an example in which occupies 7 spaces in each column.) To simplify the table, only the subscripts for the information bits are shown.

TABLE I (7L=36, It=9 l1=3) S1= (1 5 10 15 20 28 31 34) Sg= (2 5 9 14 I9 24 32 35) S3: (3 6 9 13 18 23 28 3F) S4: (4 7 10 13 17 22 27 32 S5= 8 11 14 17 21 26 31 36) S5: (4 12 15 18 21 25 30 35) S7: (3 8 16 19 22 25 29 34) Sg= (2 7 12 20 23 26 29 33) Sg: (1 G 11 16 24 27 30 33) Inspection of the table reveals certain properties in the sub-sets S1 S9 of bits. They are:

Property 1: A particular information bit appears only once in a sub-set.

Property 2: Each information bit appears in exactly two different sub-sets.

Property 3: No two sub-sets of information bits have more than one particular bit in common. This means that if a pair 0f information bits such as x1 and x5 appear in one sub-set, then no other sub-set includes both of these information bits. One other sub-set can and does include the information bit x1; a third sub-set can and does include the information bit x5.

The check bit aj for each sub-set is simply the parity bit for that sub-set. In mathematical terms, aj is the modulo 2 sum of the information bits in the sub-set Si, as shown by the following equation:

tin-:2mn forj=1, 2...9

{i655} (l) where: ieSj means all of the information bits within the sub-set Sj; and E is the modulo 2 sum.

From the properties above, one may conclude that each information bit is associated with two different check bits. This is because any information bit appears in only two sub-sets of information bits and there is a check bit associated with each sub-set of information bits. The total number of different pairs of check bits which are possible is k(k- 1)/Z. This follows from the well-known permutation-combination rules which state that if there are k bits, then there are k(k- 1)/ 2 different combinations of pairs of bits which are possible.

The minimum value of k is defined by the equation n:Mk2-1) This is simply the minimum number as, if desired, there may be more than k sub-sets. The general equation therefore is k(k-1)S2n (2) If n is given in the equation above, two different values of k are possible, One of the vvalues is negative and may be discarded. Another property of the present code is that each sub-set of information bits need not have the same number of such bits.

If k is an odd integer and is the minimum value of k, then each sub-set may have k-l bits.

If b is the length of the maximum burst-error it is desired to correct, then It also can be shown that (n4-k) -2(b-1)=B (4) where B is the total number of burst-errors of length b.

FIGURE 2 is a block circuit diagram of the circuit for generating the check bits a1, a9. Each set of information bits is applied to a parity generator and the latter generates the check bit. For example, the set of bits S1 is applied to parity generator 24-1 and it generates the parity bit a1.a1 is a 0 when there is an even number 0f ls in the sub-set S1 and al is a 1 when there is an odd number of ls in the sub-set S1.

Transmission circuit 14 The circuit 14 of FIGURE 1 transmits the Word W in segments El through E9. The segments are chosen from the table which has already been constructed. The first segment is chosen by reading down column 1. It contains the bits x1, x2, x3 and x4. The fth row of column 1 is blank and the fifth bit which is transmitted is therefore a check bit. The check bit is the one associated with the particular row in which the A appears. In this particular case, the check bit is a5. Accordingly, the first segment is x1, x2, w3, x4, a5. The next segment is taken from the next column starting with the next adjacent information bit, x5 in this particular case. Segment 2 therefore is x5, x6, xq, x8, a6. The remaining segments are E3=x9, x10, x11, x12, a7; E4=x13, Ll511, x15, x16, as; E5=x17, x13 x191 xzo, 39? E6=X2b x22, x23, X24, a1; E7=x25, x26, x27, x28, 02; Ea=x291 x30, x31, x32, as; E9: W33, X341 x35, x36, 04-

As a general proposition, each segment E is a group of contiguous information bits x1 xm followed by a check bit ap, where p for segments l, 2 k are, respectively, k+1/2, k-i-3/2 k, l, 2 k-l/2.

Syndrome generation zl, 25, 5:10, 9115, :320, zs, :1:51, :'34 and the information bit l.

If these received bits are all correct, then the syndrome bit s1=0. However, if there is a single error in a received information bit belonging to S1 or in the check bit then the syndrome bit s1 is a 1. The formal rules for calculating the syndrome bits s1 through sg are: The syndrome bit sj is equal to 1 when the information bit :zi

is within the sub-set S1 and :t1 is not equal to :ci

or when the check bit associated with Si is unequal to aj. If the information bit in error is not Within sub-set S1 and if the check bit a1 is correct, the syndrome bit s1 is equal to 0.

`So that the reader may more easily follow the rules above, they are applied below to a number of specific examples. First, assume that @wel and au other bits of w are correct. It may be seen that x1 is within sub-set S1 and therefore the syndrome bit s1=1. x1 is not within the subsets S2 S8 and therefore the corresponding syndrome bits s1 sa are all equal to 0. x1 is within the sub-set S9 and therefore the syndrome bit 111:1.

The complete syndrome therefore for the case in which there is an error in the word V^V and in which that error is in is; z(,)=z(t1)=1oo0oooo1. AS a second example, assume that the only error in the word V is the checkbit a^5. In this case, only the syndrome bit S associated with subset S5 is a 1 and all other bits are 0.

The syndrome therefore is Z (a5) =Z (1115) :000010000 It has already been stated that there can be any one of 2 b1) different errors within a sub-string of b contiguous bits of wordl If 1?;1 is considered to be contiguous to 121.45

then a word of length 45 can have 45 distinct sub-strings of length b. Thus, the total number of distinct bursterrors of length gb, for a word of length (n-l-k) is (n+k)2(b1). In the present specific example, substituting for n, k and b gives a total number of distinct bursterrors of length S3 of 180.

The syndromes corresponding to the 45 possible errors, of length 1 are shown, in part, in Table II below. yIt can be shown that the remaining 135 syndromes for burst errors of length 2 and 3 are readily obtainable from this table by adding, sum modulo 2, the syndromes for the individual bits which are in error. For example, the syndrome for 2 errors, one in bit @b1 and the other in bit 133 is Z (1111, 13)=Z (1211) G9 Z(13)= 101000101.

The syndrome for 3 errors, one in If one defines F as:

F=We3vf (5) then the F word f1, f2 f4, win have 1's in positions at which the corresponding 'w and bits are unequal, that is, where and Os in all other positions. The syndrome for an error word such as this is designated by Z(F), and is defined where A A A w1, w1 and wr are the bits in error TABLE II (1t=36; k=9) Each of the syndromes is unique, that is, it is different from any of the other 179 syndromes. In the present example, it can also be shown that for any two distinct burst-errors of maximum length b=3, the associated syndromes Z(F) and Z(F) are also distinct.

Memories used for error correction (FIGS. 4, 5 and 6) One embodiment of an error correction arrangement is shown in FIGURE 4. It includes an address decoder 28 responsive to the syndrome Z for applying an address to a read-only memory 30. In response to this address, the read-only memory produces an output 45 bit error word F which has ls in positions corresponding to the bits which are in error. This word F is added to the word W in the sum modulo 2 adder 22 to produce the corrected Word W at output cable 32.

A more detailed showing of a portion of the circuit of FIGURE 4 appears in FIGURE 5. The decoder may consist of 180 different decoder AND gates, three of which are shown at 34, 36 and 38. yEach AND gate has a certain number of inhibit inputs indicated by half circles. The decoder AND gate 34 produces an output in response to the syndrome Z 1221) that is, in response to the syndrome 100000001. AND gate 36 produces a 1 output in response to the syndrome Z(110) that is, in response to 0000101000. AND gate 38 produces a 1 output in response to The read-only memory 30 has 180 rows and 45 columns. A core of linear magnetic material, that is, magnetic material which does not exhibit a square hysteresis loop, is located at certain column and row intersections. For example, row 1 has a core 40 at column 1 and row 1. Thus, when gate 34 is enabled, a pulse appears on the row 1 lead and an output pulse appears at the column 1 sense winding 41. Under this set of conditions, the sense amplifier 44 produces an output word in which f1=l and all remaining fs are Os. In a similar manner, when gate 36 is enabled, thereby actuating core 42, a pulse appears on sense winding 4-9 and the sense amplifier produces an output f9=1 and all other fs are Os. The operation of the remainder of the circuit is believed to the straightforward. In each case an output word F is produced with ls in positions corresponding to bits which are in error. This F word is added to the W word in the sum modulo 2 adder of FIGURE 4 to obtain the corrected word.

-A modified form of circuit 20, 22 is shown in FIG- URE 6. The circuit includes content-addressed memory 50 which has an address section 52 and a data section 54. The tag applied to the memory is the syndrome Z. The output produced by the data section 54 of the memory is the error Word F. The modulo 2 adder 22 performs the same function as already described.

The content-addressed memory may be any one of a number which are well-known in the art. Many such memories have been described in literature.

Decoder Networks for Error Correction (FIGS. 7-10) fi(81, S2 51;):11'5131'52 iSk (8) The multiplication above may be defined in still another way. If the matrix of Table `II is represented by [H] then i=n+k F'lHl: 2 fi'ZUlli) The meaning of Equation 9 above can perhaps best be illustrated by a specific example. Assume that the first and second bits til and lg are both in error. In this case f1 and f2 are both 1 and all other remaining `bits of F are 0. Therefore, F [H] is one times the syndrome Z(w1) (this syndrome appears on line 1 of the matrix [H]) added sum modulo 2 to one times the syndrome Z(w2) (this syndrome appears on line 2 of the 4matrix [H] The example above may ibe expressed in terms of mathematical symbols in the following way:

It follows from the example above that Equation 9 may be rewritten as:

F-[H]=Z(F) (10) It has already been stated that in the present system the burst-errors to be corrected are of a certain specific length, namely S3. Thus, the only syndromes of interest in the present application are the result of a summation of three or less adjacent rows of the matrix [H].

There will now be considered, all of the possible bursterrors of length 53, beginning in the first seven bits of W, namely, (l, zg, :03, fn, :65, or a'). A burst-error beginning at the last bit :im scans the digits (zt, sin, 25)

and none of the bursts of length 3 which begin at bits to the left of can scan any digit to the right of 3 Thus, for an errors beginning in one of the first seven digits of W all of the possible syndromes of interest are obtainable from summation among the first nine rows of the matrix [H]. To correct these 'burst-errors therefore, it is only necessary to consider the sub-matrix of [H] consisting of the first 9 rows of [H]. As will be seen shortly, a sub-matrix of this type has been chosen because it is a square array (9 rows and 9 columns) and such arrays have special properties. This sub-matrix is hereafter identified by [G1] and it appears as Table III below.

TABLE III Z (fr) Z (lz) Z (als) Z (1,214) Z (tAvs) zeile) Z (an) Z (171s) Z600 The first 9 digits f1, f2 fg of the error word F are designated by the symbol Fa. Assuming that there are no errors in any of the bits '5010 through 1h45 Equation 10 may be rewritten vas F'[H]=F..'[G1]=Z(F) (12) Before continuing further, it is necessary to consider another type of matrix known as a unit matrix. This matrix, identified by [I] appears as Table IIV below.

TABLEIV It can be shown that for any error word Fa:

F..'[I1=l"L (14) One can derive from the matrix [G1] and the matrix [I] a third type of matrix [G1]-1 known as the inverse of [G1]. It is known from the theory of matrices that such an inverse matrix can be found uniquely in the case of square matrices like [G1] provided the square matrices satisfy a certain property known as non-singularity. It is sufficient for purposes of this present application, to know that [G1] is non-singular and for matrices like [G1] there are well dened ways of finding the inverse matrix [G1]1. (Any basic text on the subject shows how this may be done.)

The inverse matrix [G1]1 appears as Table V below.

TABLE V The multiplication of the matrix [G1] by its inverse Equation 12 may be multiplied by [G1]*1 to obtain: F1101][G1|"1=Z(F)[G1l1 (16) Substituting [I] for [G1]'[G1]1 (see Equation 15) in the left side of Equation 16 and equating this to the left side of Equation 16 gives The following equation may now be derived from Equations 16 and 17:

Z(F) [G11-1:12' [Il (18) Substituting Fa for F [I] (see Equation 14) gives:

Z(F) [G1]1=F.l (19) IEquation 19 describes the decoding scheme of interest. It states that when the syndrome for a particular error is obtained and multiplied by the inverse matrix [GQ-1, then an error word F, is obtained (the same error word Fa as appears in F of FIGURE 1) which has 1s in the positions corresponding to the bits which are in error and Os in all other positions.

To help the reader better to understand what Equation 19 means, the following specific example is given. It

may be assumed that the only bits in the received word which are in error are The above equations says that the second and eighth rows of the inverse matrix [G1]l are added, summodulo 2 (the carries are discarded) and the third and seventh rows of the inverse matrix [61]-1 are also added, sum modulo 2, also discarding the carries, and then the two sums which are obtained are added, sum modulo 2. The complete solution of the problem appears below Fa: (010000010) [G11-1@ (001000100) [G11-1 :101011101 (Row 2) @111011101 (Row 8) 001010001 (Row 3) @000010001 (Row 7) ff2e1;F1=011000000=F.x It can be seen from the above and from Equation 19 that each bit f1 making up F,z is the modulo 2 sum of the bits in the column i of Z(w1)[G1]-1. -In the specific example given, in which there are two and only two bits in error, namely in bits wz and w3:

f1=19190690=0 (addition of bits in col. 1) f2=01900=1 (addition of bits in col. 2) f3=1B1B1G90=1 (addition of bits in col. 3) f4=00900=0 (addition of bits in col. 4)

and so on.

In more general terms, expansion of the term Z (F) [G1]1 of Equation 19 gives:

@33(1 1 1 l 1 1 1 1 1)=G9ss8a se 5381811 s118380 @39(1 1 1 O 1 1 1 0 1)=Bs1sass0 s131310 sa The right hand side of the expressions above represent modulo 2 addition, where the addition is carried through along the various columns independently of eachother, that` is, with any carries which occur discarded rather than being applied to the next column. Addition of the 9 right hand columns provides the following 9 equations, where f1 is a result of the addition of column 1, f2 is a result of the addition of column 2 and so on.

Equations 20 to 28 are valid only when the bits '(1)10. LMs

of the transmitted word are all correct and when any error or burst-errors which may be present do not extend beyond the lirst nine bits However, in the most general case, this assumption may not be in order. The general equation covering errors in any of the w bits is tbm. zins are correct The circuit for implementing Equations -28 above is shown in FIGURE 7. It includes the EXCLUSIVE OR gates 61-68, respectively, and gates 71-79, respectively. (For purposes of the present simplified explanation, all of the gates 71-79, respectively are shown as AND. In practice, the first and second gates 71 and 72 and the eighth and ninth gates 78 and 79 are each a group of three gates (two AND gates followed by an OR gate) as will be discussed later in connection with 9 and 10.) The EXCLUSIVE OR gate receive the syndrome bits, as shown, and produce the error bits, as shown. Since the error bit f4' is equal to the syndrome bit s6 (see Equation 23), no EXCLUSIVE OR gate is needed for the production of the former bit.

It readily can be shown that the EXCLUSIVE OR gates do operate in the manner dened by the equations. One or two examples should suice for the explanation. EXCLUSIVE OR gate 61 produces an output slf is equal to s2EBs4Bs6Bs8- Therefore, the EXCLUSIVE OR gate 61 produces the output fy=s2s4s6s2 as desired (see Equation 20).

EXCLUSIVE OR gate 62 produces an output f2= sfg As fsf is equal to slids, f2=s4s6s2, as required (see Equation 21).

As a last example, EXCLUSIVE OR gate 65 produces an Output 525912" AS 2^=S4Sssm fs'r-szsliseesa, as required (see Equation The bits f1 fg are applied to AND gates 71 79, respectively. The second input to each AND gate is the bit v1 which is produced by the circuit of FIGURE 8. This circuit will be discussed in more detail shortly. Suice it to say, for the present, that v1=1 when there is an error of length S3, that is, a correctable error, in the received bits w1 W9. Under these circumstances, the AND gates are primed and, if a bit f is a 1, it passes through the AND gate as a l. On the other hand, if the f bit is a 0, a 0 appears at the output of the AND gate.

If there is no error which extends beyond the rst 9 information bits w1 W9, then v1 is a 0. However, under these conditions, f1 fg' are also all Os so that the adder 22 does receive all Os, as desired.

If there is an uncorrectable error as, for example, a burst-error of length 3 which extends beyond the rst 9 bits then v1 is a 0. Under these circumstances, the f bits applied to the modulo 2 adder 22 are all 0 and the word l/'l-g is uncorrected. This is a desired mode of operation as, if the error which occurs is uncorrectable, there does not appear to be any point in attempting, at least with the present system, to insert some correction.

The circuit for generating v1 shown in FIGURE 8 includes 6 OR gates 81 through 86 inclusive, 6 AND gates 87 through 92 inclusive, and an AND gate 93. The interconnection among the various gates is such that v1 is a l when there is a correctable error, that is, a bursterror of length S 3 among the first seven digits of W and a 0 at all other times.

The operation of the circuit of FIGURE 8 can be understood by considering a few examples. In the rst example, there are no errors, that is f1. fg are all 0. The last OR gate 86, under these conditions, produces an output 0. This 0 is an input to AND gate '93 so that the AND gate produces an output 111:0.

As `a second example, assume that there is a bursterror of length 3 and that this burst-error causes the error bits f3', f4 and f5' all to be 1. Under this set of conditions, OR gates 82, 83, 84, 85, and 86 all produce a l output. f1' is a 0 so that NAND gate 87 produces a 1 output. f1 and f2' are both 0 so that OR gate 81 produces a 0. This 0 output is one of the inputs to NAND gate 88 so that the latter -produces a l ouptput. f6', an input to NAND gate 89, is a 0 so that the latter gate produces a 1 output. f7', and input to NAND gate 90 is a 0 so that the latter gate produces a 1 output. f2', an input NAND gate 91, is a 0 so that NAND gate 91 produces a 1 output. 19, an input to NAND gate 92, is :a 0 so that the latter produces a 1 output. Accordingly, all of the inputs to AND gate 93 are 1 so that v1 is a 1.

Assume now that there is a burst-error of length 3 and assume that, for example, this burst-error occurs in the bits corresponding to f1=f2=f3=f4=1. As f1 and f4 are both l, NAND gate 87 produces a 0 output. This disables AND gate 93 and it produces an output 111:0.

In the discussion of the circuit of FIGURE 7, the assumption has been made that any correction bursterror does not extend beyond the ninth bit tb.,

Now the case will be considered in which the burst-error of length 3 extends beyond the first nine bits. As a specific example, assume that the burst-error occurs in bits 112s, 'fw lio To identify such errors another matrix must be drawn which includes rows having a syndrome corresponding, for example, to errors in `bit W2, wg and w10. Moreover, for present purposes, it is preferred to employ a square matrix. Such a matrix legended [G2] appears below and the inverse of this matrix [G2]1 also appears below. The matrix [G2] consists of rows y8, 9 16 of the matrix [H]. The corresponding inverse matrix [G]1 is derived from the matrix G2 in the same way as the inverse matrix [G1]1 is derived from the matrix [G1].

With the information above available, a network for implementing the equation Z[G2]-1 may be derived. This network consisting of a group of EXCLUSIVE OR gates analogous to EXCLUSIVE OR gates 68 of FIG- URE 7 but arranged to satisfy the terms of the equation Z '[G2] 1- In a manner similar to the above, additional networks are formed making use of the other [G] matrices and their inverses, all of these matrices being listed below as Table VI.

TABLE XVI-Continued 010000100 000100010T 100000010 001000101 000000001 010101010 [ROWS 22 to 30 0f [H]= [G.1]= 000011000 [041-1: 101010101 000100100 101000101 001000010 010100010 010000001 001000001 100000000 000100000- 010000001- '010000000 100000000 000000100 000001100 010001000 000010010 100010100 [ROWS 29 to 37 0i [H]=[G5]= 000100001 [G5]1= 101100111 101000000 100000101 010000000 101000101 000000110 101000111 000001001 100000100- "000000110- '001010001' 000001001 111011111 100010000 000010000 010100000 111111111 [Rows 36 to 44 of [H]=[G]= 001000000 [G,]-1= 000010001 000000011 111011101 100000100 001010101 010001000 101010101 001010000 101011101- "010001000 101000101 001010000 101000100 000100000 010000010 100000001 001000000 [Rows 43 to 6 of [H]=[G7]= 010000010 [G7]1= 000000010 001000100 001000100 000101000 010001010 000010000 101010100 110000000 101100101.

FIGURE 9 illustrates the complete decoder system employed to implement the block 20 of FIGURE 1. There are seven circuits 101-107 for generating the seven v bits v1 v7, respectively. There are seven networks, shown at 111 through 117, respectively, for solving the equation Z-[GQ-1 where i=1, 2 7. The circuit 101 is the circuit of FIGURE 8. The circuits 102-106 are essentially identical with the circuit of FIGURE 8, however, with diiTerent error bits f1 applied. For example, in the circuit 102 for v2 the error bits f8 and fg are applied to OR gate 811 rather than the bits f1 and f2. The bit 'fle' is applied to NAND gate 92 rather than the bit fg' and so on. Similar substitutions are made in the other circuits.

The v7 circiut 107 is similar to the circuit of FIGURE 8 with two minor modifications. The line 118 is deleted and the dashed line 119 is added.

The network 111 is the network of FIGURE 7 with some modications in the gates 71-79. Rather than employing a single AND gate 71 for the first gate, the gates of FIGURE 10a are used. The gate 120 receives the bits v1 "and the bit f1 from network 111, that is, from the EXCLUSIVE OR gate 61 (FIGURE 7) within network 111. If there is a burst-error of length g3 that begins with f1', then gate 120 will produce an output f1. This is the operation desired.

It may be that 101 is an error is part of a burst that begins with the last bit 12145 or with the next to the last bit 'vn of the word W but that this error l blt 1044 01 1045 t0 Ll The outputs of AND gates 120 and 121 are applied through OR gate 122 to the modulo 2 adder 22. This bit is the bit f1.

The second gate, corresponding to 72 of the network 14 117, is shown in FIGURE 10b. It comprises two AND gates 123 and 124 connected to an OR gate 125. This small network serves to produce the error bit f2, taking into account a burst-error of length S3 which either starts at bits w1 or wz or which starts at bit w45.

rThe last two gates, corresponding to 78 and 79 of FIGURE 7 of each network Z[Gi]-1, are shown in FIGURES 10c and 10d, respectively. The next to last gate, corresponding to 78 of FIGURE 1, includes two AND gates 126 and 127 followed by an OR gate 129. The first gate 126 corrects for a burst-error of length 3 which starts in the third from the last bit. For example, in the case of network 111, which produces error bits f1 fg corresponding to the bits 101 vg gate 126 corrects for any error of length S3 which starts with bit 107 In the event of such an error and if in fact the bit 108 is in error, then v2 will be 1 and AND gate 126 will produce an output equal to fs. It should be noted here that FIGURE 10c is general and that in the case of network 111 j=0 so that vj+1 is equal to v1 and f8+9, is equal to If the burst-error of length S3 extends beyond bit wg and starts at bit f8 in this particular example, then AND gate 127 corrects for this error. This gate, in this particular example, receives the input f8 from network 112 and the input v2 from network 112 and produces an output which is equal to f8. Again, note that in the example of network 111, j=0 so that f'8+7j=f8.

From the explanation above, the network of FIGURE 10d should be self-explanatory. In the case of FIGURE 1, it produces the corrected output fg for correctable bursts. In the case of network 112 it produces the output fw for correctable bursts an so on.

It should be noted that in the arrangement of FIGURE 9 the convention is adopted that the network 111 produces outputs f1 fg, a total of 9 error bits. The networks 112-116 each produces only 7 errors bits. In each of these networks, the f bit producing circuits for the rst 5 stages employ a single AND gate such as 73 of FIG- URE 7. This AND gate receives the bits f1 and vi and produces the output f1.

The last network 117 is required only to produce the bit 13,5 and an output the bits 143 and f4.1' to be fed back to network 116, and the bits f1 and f2' to be fed back to network 11. It does so by means of the appropriate EXCLUSIVE OR gates and a single AND gate analogous to 73.

Serial System In the systems discussed up to this point, the word W is transmitted in parallel, that is, all the bits are transmitted at the same time. In the system to be discussed now, the bits are transmitted serially and the decoding is performed in a serial manner. While this method of operation requires more time, it needs less equipment.

Again, before proceeding to the circuit, it is necessary to introduce some additional principles of matrix mathematics. In the serial decoder, using the same example as above, namely, a word with 36 information bits and 9 check bits, the matrices [G1] and [G1]-l are chosen as before. In addition, the following 9 matrices are chosen:

[G9']=[rows 41 45, 1 4 of [H1] Table VII below is inserted for the purpose of showing the inter-relation among the various [G] matrices.

TABLE VII In a similar manner, i=2 9is the general equation for It can also be shown, for =2 9, [G'] given by Equation 31; and [G1]1 given by Equation 14a; that:

where D(i 1)[G1]*1 denotes a downward cyclic shift of the rows of [G11-1 through (-l) rows. Put in other words, a downward cyclic shift, for example, of l is the rearrangement of rows 1 through 9 of [G1]-l in the order 9, l, 2 8.

Employing an analysis similar to that used in obtaining Equation 19, it can be shown that:

Z(F) [Gil=Z(F) D i-1 [G1l1 =(Si+1, Si+2...s9, S1,Si)[G1l-1 (34) where (sm, s1+2 sg, s1 s1) is obtained from (s1 S9) =Z by a cyclic left shift of z' digits.

In a manner similar to that employed in connection with Equation 19, one may define:

The network of FIGURE 12 may now be employed to determine from Fi whether there is a burst of length S3 with a 1 among the rst five digits. If there is such a burst, then v1 will be a 1. The operation of this network is believed to be self-evident from the explanation of the operation 0f the network of FIGURE 8. A few examples will suffice for the explanation. First, assume that f is a l and f1.1 is also a 1. In this case, NAND gate 150 produces "a O output and v1 is a 0. If, on the other hand, fn is a 1 and fm fig are all 0, then all NAND gates 150-155 produce a 1 output and v1 will equal a 1.

A complete system which employs serial transmission and serial decoding is illustrated in FIGURE 11. A clock pulse source 450 produces 1 clock t1 each unit of time. The pulses t1 are applied to a l to 45 counter 451 which applies its output to the count of 44 decoder 452, and the count of 45 decoder 453. When the count of 44 is reached, the count of 44 decoder produces an output which is applied to the set terminal of flip-flop 454. The output obtained from the flip-Hop in its set condition disables the count of 44 decoder 452 and actuates the pulser 455. The latter produces an output pulse which resets the 1 to 45 counter 451. The output pulse produced by the count of 44 decoder 452 is also applied to OR gate 456-.

The clock pulses t1 are also applied to a l to 5 frequency divider 457. The latter produces l output pulse t5 every fifth input pulse it receives.

' A The input information pulses w1 occur serially in synchronism with the clock pulses t1. These information pulses are applied to a switch 156. The switch is normally open but is closed in response to each clock pulse t1. Thus, each information pulse tin is applied through the switch 156 both to a 45 stage shift register 158 and a stepping or commutator switch 160.

The input bits are shifted from stage-to-stage of shift register 158 in response to the clock pulses t1. Accordingly, after 45 time intervals, that is, after 45 Iclock pulses t1, the shift register 158 is entirely loaded, as shown schematically in the figure.

The formation bits w, passing through switch 156. are applied by the stepping switch 160 to a 5-stage register 162. The stepping switch initially connects switch 15610 the first or uppermost stage of register 162. Each clock pulse t1 serves to step the switch to the next stage of register 162. Thus, after the rst clock pulse, the stepping switch connects to the second stage of the register and so on.

After the first 5 received pulses the register 162 is fully loaded. It stores the bits 1211 through z,

reading from top to bottom. The 6th information pulse is applied by the stepping switch 160 to the first stage of the register so that after the 6th clock pulse t1, the register stores the bits tzg, '652. .'n. After the 45th time interval, the register 162 is loaded with the bits as shown schematically in FIGURE 1l.

The register 162 is connected through 5 switches, illustrated by a single block 164, to the 9-stage serial adder 166. The switches are normally open but are closed each 5th time interval by the timing pulse t5.

Each stage of the serial adder 166 consists of a storage circuit (ST), such as 167, followed by an EXCLUSIVE OR gate, such as 168. The storage circuit is shown in more detail in the legend of FIGURE 11. It includes a set-reset ip-op 169, an AND gate 170 connected to the set terminal of the ipflop and a NOR gate 171 connected to the reset terminal of the ip-flop. The timing pulse t5 serves as a priming signal for AND gate 170 and is also applied through inverter 172 as a priming signal for NOR gate 171. The input information from an EXCLUSIVE OR gate is applied via lead 173 both to the NOR gate 171 and the AND gate 170. The 1 output terminal of flip-flop 169 is connected through a delay means 174 to 1 input to the following EXCLUSIVE OR gate. The delay At which is inserted is less than one unit of time and, in fact, less than the interval of pulse t5. The purpose of the delay is to give each EXCLUSIVE OR gate in the adder 162 suliicient time to apply the information applied to it by a storage circuit ST preceding that gate to the storage circuit following that gate.

The connection of the register 162 through the switches 164 to the serial adder 166 is such that after the initial 5 units of time the serial adder stores the information hits )1...}5 III the OTCIQI @1, (272, }3, 1,174, '}5, 604, @3, '1?)2 @1. This corresponds to the data in column 1 of Table I on page 6 of this specification, with i5 substituted for )c The serial adder 166 is connected through 9 switches, illustrated as a single block 181, to the 9-stage shift register 190. The switches are normally open and are closed one interval of time after the pulse IR occurs. The one unit delay is inserted by delay means 191.

The shift signal for the register 190 is the timing pulse t5. Each time this timing pulse occurs, the information present in the register is shifted one place to the left. The register is reset by the timing pulse tR.

Register 190 is connected to the network 192 for calculating Z [Gil-1. The output of this network is applied through 9 switches, illustrated by a single block 194, to a 9-stage shift register 196. The switches are normally open, however, under certain conditions (discussed later), they are closed -in response to an output from AND gate 195 each time pulse t occurs. The information present in register 196 is shifted to the right in synchronism with the clock pulses t1.

The output of switches 194 is also applied to circuit 198. The latter is the circuit of FIGURE 12 and it produces the output vi. As previously mentioned, v1 is a 1 in 9 the case of a correctable error and a 0 at all other times.

The signal v1 is applied to the set terminal of flip-flop 200 and to one input of AND gate 202. The output of flip-flop 200 is applied to AND gate 204, to 7 unit delay means 206, and to inverter 208. The output of the circuit 206 is applied through an -OR gate 210 to the reset terminal of flip-flop 200 and is also applied directly to the set terminal of flip-flop 212.

The output of inverter 208 is applied to AND gate 195. The output of AND gate 195 is applied to control switches 194 and also to trigger the modulo 9 counter 214. The output of the modulo 9 counter 214 is applied to an AND gate 216. The second input to this AND gate is the output of a ip-op 218. The output of AND gate 216 is applied to an OR gate 220.

Returning for a moment to the 9-stage shift register 190, the bit stored in the leftmost stage of this register is applied through a 1 unit delay means 222 to the set terminal of flip-flop 218.

In the operation of the circuit of FIGURE ll,

the imput signals 'v are applied serially to the 45-stage shift register 158. After 5 intervals of time, 5 of the bits }5 h are stored in the shift register 158. The same 5 bits are stored in the S-Stage register 162. At that time the pulse t5 occurs and the 5 bits in register 162 are applied via the now closed switches 164 to the serial adder 166.

After another 5 intervals of time, the bits vro, wg are stored in register 158. The information bits 1215 iw are stored in register 162. The bits stored in the adder 166 are shifted one place to the right. The serial adder 166 therefore is storing the bits il through 1215 in the following order:

1l,bly vly @27 7b3; 'Mf @Si @4: 'Sy 1'b2- At this same time, the second pulse t5 closes switches 164. This causes the next 5 information bits lg to be applied to the EXCLUSIVE OR gates of the adder so that the EXCLUSIVE OR gates add the new information with the previously stored information.

The new information is applied to the 9 stages of the serial adder 166 in the following order:

'ly ib?, @Si @Si @10: M?) @Si @A071 w6- As already mentioned, the old information is present in the first through the 9th stages in the order A A A A A A A A rtl, w1, wz, w3, w4, 105, wl, w3, w2-

18 Accordingly, the adder performs the addition of This addition corresponds exactly to the addition of the first two bits, respectively, in each row of Table I.

'il corresponds to the numeral l in column l, row l of Table I and we to the numeral 5 in column 2, line l corresponds to the numeral 1 in column l, line 9 of Table I and (which is 51.-) corresponds to the numeral 6 in column 2, line 9. As a third example,

n (which is the check bit corresponds to )t in column l, row S of Table I and lg (which is the information bit g) .corresponds to the numeral 8 in column 2, row 5 of Table I.

The steps above continue until, after 45 time intervals, the adder 166 has obtained the sum of every row in Table I, substituting a check bit wherever A appears in the table. The adder 166, in other words, has performed, in serial fashion, precisely the same function as the syndrome generator shown in FIGURE 3 performs in parallel fashion. The result of the addition is the syndrome Z=S1 Q S9.

At the 44th time interval, the timing signal tR occurs. This signal is delayed one additional interval by the one unit delay circuit 191 so that at the 45th time interval the switches 181 close. The closed switches apply the syndrome Z=s1 s9 to the 9-stage shift register 190. Immediately prior to the receipt of this information, the register was cleared by the reset signal tR which, it will be recalled, occurs at the 44th unit of time.

As the syndrome is available, the circuit 192 can now compute Z [GQ-1. The EXCLUSIVE OR gates for doing this are precisely the EXCLUSIVE OR gates of FIG- URE 7. The error bits thereby obtained are applied to the switches 194 which are closed (this is discussed later).

The switches 194 apply the error bits to the shift register 196 and also to the circuit 198. The circuit 198 is the one shown in greater detail in FIGURE ll, that is, it is the circuit for calculating whether there is a bursterror of length 3. If there is, then vi, which in this particular case is v1, is a l. If v1 is a l, it sets flip-flop 200 which produces a priming signal for AND gate 204. If at the same time f1' is a l, then AND gate 204 produces a l output (an error signal x l) which serves as one input to EXCLUSIVE OR gate 230 at the upper part of the figure. Due to various delays inthe circuit, this error signal a, if it is present, occurs after a delay interval yAt, the same delay as inserted by delay circuit 232. Therefore, when the error signal a is applied to EXCLUSIVE OR gate 230, a bit stored in the shift register,

the bit il in this particular example,

is also applied to the EXCLUSIVE OR gate. The bit in this way automatically is corrected and a corrected output i121 appears at output lead 234.

After 5 intervals of time, the syndrome Z=s1 s9 is cyclicly shifted one place to the left by the timing pulse t5. The shifted syndrome bits are now applied to the network 192 so that, for example, EXCLUSIVE OR gate 71 of FIGURE 7 receives the bit s2 rather than s1, EXCLUSIVE OR gate 65 receives the bit s3 rather than s2 and EXCLUSIVE OR gate 66 receives the bit s1 rather than s9. The effect of all of this is to make the network 192 solve Equation 34, that is, solve the equation Z [612]-1. This permits the network to compute the error bits fsf-f1.1. These error bits permit the information bits i. .12110 to be corrected in the same manner as already discussed in connection With the error bits 1111. .$05.

The circuit of FIGURE 11 continues to operate until all 45 error bits have been corrected. To summarize, after 45 time intervals, the 45 stage shift register is fully loaded and the syndrome is calculated. After 45 additional delay intervals, if there is a burst-error which is correctable, it has been corrected. During this additional 45 delay intervals, a second Word W2 can be received and loaded into the shift register 158. During the third 45 delay intervals, this second word can be processed in the same manner as already discussed.

A number of the circuit elements shown at the bottom of the ligure are for indicating correctable or noncorrectable errors. lf v1 is a l, indicating a correctable error, ip-ilop 200 become set and AND gate 204 is primed. Also, AND gate A202 is primed. When Hip-flop 200 is set, the inverter 208 applies `a disabling signal to AND gate 195. The flip-flop 200, once set, remains set for at least 7 time intervals and therefore AND gate 195 remains disabled for this same period. Therefore, for 7 time intervals, at least, the AND gate 195 maintains the switches 194 disabled. On the other hand, if vi is a 0, Hip-flop 200 is not set, AND gate 195 is primed, and each th time interval the pulse t5 passes through AND gate 195 and causes switches 194 to close.

If v is a 1 and flip-op 200 becomes set, then after 7 time intervals, the delay means 206 produces an output. This output passes through OR gate 210 Iand resets the flip-ilop 200. This output is also applied directly to the set terminal S of flip-nop 212 and the latter applies a priming signal to AND gate 202.

It should be recalled at this point that the present circuit is capable of correcting only a single burst-error. Therefore, if after one burst-error has occurred and flipop 200 has become set, and then reset and then another burst-error occurs, the circuit should indicate that the second burst-error is uncorrectable. It does this by means of the circuit just described. The second burst-error causes vi to become l again. AND gate 202 is primed by the set iiip-iiop 212. The second vi=1 therefore passes through AND gate 202 and OR Igate 220. The output of this OR gate is a signal indicating an uncorrectable error.

If the output vi is never a l, within a 45 unit time interval and 51:1, this indicates that there is an uncorrectable error. Should this occur, the s=l output of register 190 occurring sometime during the 45 unit time delay passes through delay means 222 and sets flip-flop 218. The output of this ip-flop serves as a priming signal for AND gate 216. The modulo 9 counter produces an output after eight pulses t5 have been applied thereto by AND gate 195. (The ninth pulse resets the counter to zero). This output is applied as the second input to AND gate 216 and serves to enable this gate. The enabled AND gate 216 applies an uncorrectable error signal to OR gate 220. This same signal (UE) may be used also to reset the MOD 9 counter.

General Remarks While for purposes of illustration, the invention has been illustrated for the case in which 11:36, k=9 and b=3 the invention is, of course, of more general applicability. The tables which follow illustrate the way in which the subsets may be chosen for other illustrative values of n, k and b. The circuits employed for the system, in any particular case, while differing in detail from the speciiic circuits illustrated, follow the design criteria outlined herein and operate in the same way as the circuits shown and described herein.

followed by a check bit ap TABLE VIII (n=78; k=13; b=5) [Check Bits: ai=2zi1; i=1 .13]

Z'eSi S2 2 7 13 20 27 34 4l 4S 60 65 70 75 Se 6 11 16 21 26 31 37 44 5l 58 65 72 )t Code Work W=91 Digits= 12313317 3231.163336 tanti?? TABLE IX (11:39; k=13; b=3) su -,159 1 i 1 1. i i A33 35 37 Code Word W=52 Bits= fixez-3am Jarman messina Seg- Seg- Segnient; l ment 2 meut 13 TABLE X (n=21; k=7; b=2) Code Word W=28 Bits As a general proposition, each segment E, in this case, 1s also a group of contiguous information bits x1 xm where p for segments 1,

21 2 k are, respectively, (k-b-l), (k-b) k, 1, 2 (k-b-2) and b:[the largest integer In the previous discussion, attention is given to the example given by the matrix [V] in Table I. All the considerations are identical for both the cases illustrated by Tables I and IX. In the case of codes with more than one empty space per column of [V] there is a small difference in the correction procedure, as discussed below.

In the case of codes in the type shown in Table IX, the matrix [G1] (corresponding to Table III on page 16) will be of the form shown in Table Xl below.

TABLEXI This matrix is not rectangular. However, if the zeros indicated in the dashed rectangle in Table XI are removed, a rectangular matrix [H] is obtained, as rshown as shown in the Table XIII.

TABLEXIII And the matrix [G]1 is then as shown in Table XIV.

TABLEXIV 22 In Equation 19 (page 18) the errors beginning in the first segment of the code word Fa, were obtained by forming the product Fa=Z(F)-[G1]1. In the present case, a new product Z (F)*[G1]1 is defined, as follows:

where Z(F)=(s1 s2 cal OR.

This "t product is in effect the union (Logical OR) of the earlier defined product and the term S13) and V stands for logi- If all the errors within the digits are included in [G1] (the first 8 digits of the code Word), then s1=0 for i=5 9. (Notice that [G1] has zeros in columns 5 to 9.) Therefore,

If all the errors are not within the first eight digits of the code word then Z( F) [G1]1 will be a burst of length 3.

The irst part of the network comprising the product will be the network corresponding to the product. Let

and

Z(F)*[G1l1be(f1f2 fi'f) The middle six bits of the product will be the same as the middle six digits of the product. The two end bits f1 and f8 are obtained as follows:

All the remaining operations of decoding in the two cases are exactly analogous.

As mentioned previously, k is an odd integer. For k=9 or k=a prime number 9 the number of empty spaces )1 in the matrix of sub-sets [V] is just 1. In these cases each code word will have k(k1)/2 information digits. For k=a prime 79, the number of information digits in a code word with k check digits and the maximum length of a correctable burst-error are listed in the Table XV.

For any k9, if k is an odd number then another code may be defined in which the number of empty spaces in each column of the matrix [V] is given by [k-Zb] where b is the maximum correctable burst-error length for the code, and

b [the largest integer S TABLE XV A list of EBEC-codes when the number of cheek digits, k, is a prime 1l gk 7.9

Number of information Number digits: of cheek MIJ-1) digits: k 2

Max. correctable burst length 11 13 17 1.) 2d Z9 l 37 41 43 47 53 l) 6l 67 71 73 79 What is claimed is:

1. A system for correcting errors in a string of bits x1 xn comprising, in combination:

means for selecting k sub-sets S1 of said information bits such that an information bit appears only once in a particular sub-set, each information bit is included in two sub-sets, and no two sub-sets contain the same pair of information bits;

means for generating a check bit for each said sub-set of information bits;

a transmitting circuit receiving inputs from said means for selecting and from said means for generating, and providing a word W consisting of a string of said n bits arranged in segments, each segment containing a group of different information bits, less in number than the bits of a sub-set, and a check bit, each information bit of a segment being chosen from a different sub-set and said check bit being that of another sub-set; A

means receptive of the word W for generating a syndrome Z `which has bits all of the same value when there is no error in the received bits and which has a distinctive pattern of Os and ls indicative of a burst error of length 5b if there is such an error;

memory means responsive to the syndrome Z for producing a binary error word F which has bits of one value in positions corresponding to those occupied by bits of word W which are not in error, and bits of the other value in Y positions corresponding to those of bits of word W which are in error; and means responsive to the word W and to the error word F for producing a corrected word W,

where:

n in an integer kA and b are integers which are smaller than n, W is the `word W, as received, and may or may not be equal to W` 2. A system as set forth in claim 1 wherein said memory means comprises a decoder responsive to said syndrome for producing a memory address, and read-only memory means responsive to said address for reading out, in parallel, the bits of said error word.

3. A system as set forth in claim 1 wherein said memory means comprises a content-addressed memory.

4. A system for correcting errors in a string of bits x1 xn comprising, in combination:

means for selecting k sub-sets S1 Sk of said information bits, ywhere S1 S1z are rows in a matrix [V] having k columns and k rows, the first column V1 of which consists of information bits having the subscripts: 1, 2 t, t 2; 1 and each succeeding ith column V1 of which consists of information bits having the subscripts r(-1)+1, r(i-1) ri, i, zi, .ui-1), t(z'-1){1, cyclicly shifted down through z' rows, where: i=1, 2 k; indicates an odd number of empty spaces; t is less than k/2; and, k is an odd integer;

means for generating a parity check bit for each said sub-set of information bits;

a transmitting circuit receiving inputs from said means for selecting and from said means for generating, and providing a word W consisting of a string of said n bits arranged in segments, each segment containing a group of different information bits less in number than the bits of a sub-set and a check bit, each information bit of a segment being chosen from a diffe-rent sub-set and said check bit being that of yet another sub-set;

means receptive of the vword W for generating a syndrome Z which has bits all of the same value when there is no error in the received bits and which has a distinctive pattern of Os and 1s indicative of a burst-error of length Sb if there is such an error; and

means responsive to the word W and to the syndrome Z for producing a corrected word W;

where:

nA is an integer larger than k W is the word W, as received, and may be equal or unequal to W, and b is an integer which is smaller than n.

5. The system set forth in claim 4 wherein each i'th segment comprises the t information bits in column i of matrix [V] and the check bit is aj, the check bit for sub-set Sj, where j identities a row of column z' in which A appears, where j=1, 2 k.

References Cited UNITED STATES PATENTS 3,246,315 4/1966 Gear 340-166X OTHER REFERENCES W. W. Peterson, Error-correcting Codes, pp. 231- 234, MIT Press and John Wiley & Sons, Inc., New York, 1961.

MALCOLM A. MORRISON, Primary Examiner R. S. DILDINE, JR., Assistant Examiner 

